1. Field of the Invention
The present invention relates to integrated circuits having buffers for driving external or internal loads.
2. Description of the Prior Art
Integrated circuits have variations in operating speed due to various factors, including variations in the manufacturing process, and variations in the operating temperature and power supply voltage. CMOS integrated circuits typically have a variation of about three in speed between the worst-case fast (WCF) and worst-case slow (WCS) conditions. The effect of this variation on output buffers, especially transistor-transistor logic (TTL) level buffers, is that when the buffer is sized for a certain maximum propagation delay at WCS conditions, it is about three times faster at WCF. This makes it so fast that the high rate that it switches current through the package inductance, L, generates a large voltage equal to L.times.(di/dt). When the buffer output rises, the effect is to cause the power supply voltage (V.sub.DD) to dip below its normal value. When the output falls, the effect is to cause V.sub.SS to rise above its normal value, which is called "ground bounce". In practice, it is this second case that causes the most problems on TTL buffers. The TTL threshold of 1.5 volts is far enough below V.sub.DD /2 so that the N-channel output device must be much larger than the P-channel to obtain equal rise and fall propagation delays. Also the 1.5 volt threshold makes TTL input buffers much more susceptible to V.sub.SS bounce than to V.sub.DD bounce. If V.sub.SS (nominally ground) rises above about 1.5 volts at a TTL input which is held at 2 volts (minimum VIL specification), the input buffer will glitch. Still other noise problems are possible due to excessively fast rise and/or fall times of the output buffer.
Attempts to automatically control ground bounce typically rely on creating analog control voltages which vary the magnitude of the drive signal on the gates of the output transistors. For example, one such technique is shown in U.S. Pat. No. 4,823,029, and another is shown in U.S. Pat. No. 5,017,807, both co-assigned herewith. Although successful in many applications, these analog control voltages are typically generated by circuits whose modeling depends on the accuracy of the modeling of the manufacturing process. In many cases, this modeling is not accurate enough to produce reliable control voltages, especially when changes in the manufacturing process occurs. Also, the analog control voltages being bussed around the chip can be influenced by local noisy signals as they cross over the conductors carrying them. Another technique is to include an additional pull-down (or pull-up) output transistor for sinking (or sourcing) additional output current. The additional transistor is activated when the voltage on the buffer output node passes a given threshold; see, for example, U.S. Pat. No. 5,097,148 co-assigned herewith.